|
| enum | IN_SEL : uint8_t {
VCM_VCM = 0
, AIP_AIN
, AIP_VSNS
, GPIO0_GPIO1
,
AIP
, AIN
, ISNS
, VSNS
,
TIA
, GPIO0_VCM
, VCM_GPIO1
, REF_BYP__VCM
,
VCM__REF_BYP
, BG
, VADD
, LDO
,
VHDD
, VHSS
, DAC_REF
} |
| enum | GainPGA : uint8_t { G_PGA_x_1_0
, G_PGA_x16_0
} |
| enum class | Register16 : uint16_t {
CRC_CONF_REGS = 0x20
, CRC_COEF_REGS = 0x21
, CRC_TRIM_REGS = 0x22
, CRC_TRIM_REF = 0x3F
,
GPI_DATA = 0x23
, GPO_ENABLE = 0x24
, GPIO_FUNCTION = 0x25
, GPI_ENABLE = 0x26
,
GPI_EDGE_POS = 0x27
, GPI_EDGE_NEG = 0x28
, GPO_DATA = 0x29
, SYS_CONFIG = 0x2A
,
SYS_STATUS = 0x2B
, CK_SRC_SEL_CONFIG = 0x30
, GLOBAL_ALARM_ENABLE = 0x2C
, GLOBAL_ALARM_INT = 0x2D
,
DIE_TEMP = 0x2E
, TEMP_THRS = 0x2F
, PN2 = 0x40
, PN1 = 0x41
,
PN0_REV = 0x42
, AI_CONFIG0 = 0x1000 | 0x20
, AI_CONFIG1 = 0x1000 | 0x21
, AI_CONFIG2 = 0x1000 | 0x22
,
AI_MULTI_CH_EN = 0x1000 | 0x23
, AI_SYSCFG = 0x1000 | 0x24
, AI_STATUS = 0x1000 | 0x25
, AI_STATUS_OVR = 0x1000 | 0x26
,
AI_STATUS_UDR = 0x1000 | 0x27
, AIO_CONFIG = 0x1C00 | 0x20
, AO_CAL_COEF = 0x1C00 | 0x21
, AIO_PROT_CFG = 0x1C00 | 0x22
,
AO_SLR_CTRL = 0x1C00 | 0x23
, AWG_PER = 0x1C00 | 0x24
, AO_SYSCFG = 0x1C00 | 0x25
, AIO_STATUS = 0x1C00 | 0x26
} |
| enum class | Register24 : uint16_t {
GAIN_COEF0 = 0x50
, GAIN_COEF1
, GAIN_COEF2
, GAIN_COEF3
,
GAIN_COEF4
, GAIN_COEF5
, GAIN_COEF6
, GAIN_COEF7
,
OFFSET_COEF0 = 0x58
, OFFSET_COEF1
, OFFSET_COEF2
, OFFSET_COEF3
,
OFFSET_COEF4
, OFFSET_COEF5
, OFFSET_COEF6
, OFFSET_COEF7
,
EXTRA_CAL_COEF0 = 0x60
, EXTRA_CAL_COEF1
, EXTRA_CAL_COEF2
, EXTRA_CAL_COEF3
,
EXTRA_CAL_COEF4
, EXTRA_CAL_COEF5
, EXTRA_CAL_COEF6
, EXTRA_CAL_COEF7
,
SERIAL1 = 0x43
, SERIAL0
, AI_DATA0 = 0x1000 | 0x30
, AI_DATA1
,
AI_DATA2
, AI_DATA3
, AI_DATA4
, AI_DATA5
,
AI_DATA6
, AI_DATA7
, AI_CH_OVR_THR_0 = 0x1000 | 0x38
, AI_CH_OVR_THR_1
,
AI_CH_OVR_THR_2
, AI_CH_OVR_THR_3
, AI_CH_OVR_THR_4
, AI_CH_OVR_THR_5
,
AI_CH_OVR_THR_6
, AI_CH_OVR_THR_7
, AI_CH_UDR_THR_0 = 0x1000 | 0x40
, AI_CH_UDR_THR_1
,
AI_CH_UDR_THR_2
, AI_CH_UDR_THR_3
, AI_CH_UDR_THR_4
, AI_CH_UDR_THR_5
,
AI_CH_UDR_THR_6
, AI_CH_UDR_THR_7
, AO_DATA = 0x1C00 | 0x28
, AO_OC_POS_LIMIT
,
AO_OC_NEG_LIMIT
, AWG_AMP_MAX
, AWG_AMP_MIN
} |
| enum | Command : uint16_t {
CMD_CLEAR_ALARM = 0x12
, CMD_RESET = 0x14
, CMD_CLEAR_REG = 0x15
, CMD_RELOAD = 0x16
,
CMD_CALC_CRC_CONFIG = 0x2006
, CMD_CALC_CRC_COEF = 0x2007
, CMD_CALC_CRC_FAC = 0x2008
, CMD_CH0 = 0x1000
,
CMD_CH1 = 0x1001
, CMD_CH2 = 0x1002
, CMD_CH3 = 0x1003
, CMD_CH4 = 0x1004
,
CMD_CH5 = 0x1005
, CMD_CH6 = 0x1006
, CMD_CH7 = 0x1007
, CMD_ADC_ABORT = 0x1010
,
CMD_END = 0x1012
, CMD_CLEAR_DATA = 0x1013
, CMD_SS = 0x3000
, CMD_SC = 0x3001
,
CMD_MM = 0x3002
, CMD_MC = 0x3003
, CMD_MS = 0x3004
, CMD_BURST_DATA = 0x3005
,
CMD_WGEN_STOP = 0x1C00
, CMD_WGEN_START = 0x1C01
, CMD_CLEAR_DAC0 = 0x1C02
, CMD_AO_ABORT = 0x1C03
,
CMD_AO_ABORT_HIZ = 0x1C04
, CMD_CISW_ABORT = 0x1C05
, CMD_CISW_ABORT_HIZ = 0x1C06
} |
| using | ch_setting_t = uint16_t[ 4 ] |
| enum | LV_mux_sel : uint8_t {
REF2_REF2 = 0
, GPIO0_GPIO1
, REFCOARSE_REF2
, VADD_REF2
,
VHDD_REF2
, REF2_VHSS
, HV_MUX
} |
| using | raw_t = int32_t |
| using | volt_t = double |
| typedef void(* | callback_fp_t) (void) |
|
| | NAFE33352_Base (bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC) |
| virtual | ~NAFE33352_Base () |
| virtual void | boot (void) |
| virtual void | reset (bool hardware_reset=false) |
| virtual void | open_logical_channel (int ch, uint16_t cc0, uint16_t cc1, uint16_t cc2, uint16_t dummy) |
| virtual void | open_logical_channel (int ch, const uint16_t(&cc)[4]) |
| void | open_dac_output (const uint16_t(&cc)[6]) |
| virtual void | close_logical_channel (int ch) |
| virtual void | close_logical_channel (void) |
| void | enable_logical_channel (int ch) |
| virtual void | start (int ch) |
| virtual void | start (void) |
| virtual void | start_continuous_conversion () |
| virtual void | DRDY_by_sequencer_done (bool flag=true) |
| virtual raw_t | read (int ch) |
| virtual void | read (raw_t *data) |
| virtual void | read (volt_t *data) |
| double | raw2v (int ch, raw_t value) |
| virtual void | dac_out (double vi, double full_scale, uint8_t bit_length) |
| int32_t | dac_code (double a, double full_scale, uint8_t bit_length) |
| virtual void | command (uint16_t com) |
| virtual void | reg (Register16 r, uint16_t value) |
| virtual void | reg (Register24 r, uint32_t value) |
| virtual uint16_t | reg (Register16 r) |
| virtual uint32_t | reg (Register24 r) |
| template<typename T> |
| uint32_t | bit_op (T rg, uint32_t mask, uint32_t value) |
| uint64_t | part_number (void) |
| uint8_t | revision_number (void) |
| uint64_t | serial_number (void) |
| float | temperature (void) |
| | AFE_base (bool spi_addr, bool highspeed_variant, int nINT, int DRDY, int SYN, int nRESET, int DRDY_input, int SYNCDAC) |
| virtual | ~AFE_base () |
| virtual void | begin (void) |
| virtual void | set_DRDY_callback (callback_fp_t fnc) |
| virtual raw_t | start_and_read (int ch) |
| template<typename T> |
| void | start_and_read (T data) |
| double | raw2uv (int ch, raw_t value) |
| double | raw2mv (int ch, raw_t value) |
| double | drdy_delay (int ch) |
| double | drdy_delay (void) |
| int | enabled_logical_channels (void) |
| void | use_DRDY_trigger (bool use=true) |
| void | txrx (uint8_t *data, int size) |
| void | write_r16 (uint16_t reg) |
| void | write_r16 (uint16_t reg, uint16_t val) |
| uint16_t | read_r16 (uint16_t reg) |
| void | write_r24 (uint16_t reg, uint32_t val) |
| int32_t | read_r24 (uint16_t reg) |
| void | burst (uint32_t *data, int length, int width=3) |
NXP Analog Front End class library for MCX
- Author
- Tedd OKANO
Copyright: 2026 Tedd OKANO Released under the MIT license
Definition at line 16 of file NAFE33352.h.